Many high performance circuits such as, for example, microprocessors, use static flip-flops. Such a circuit typically has a large number of flip-flops with groups of logic gates connected between flip-flops, with the flip-flops operating to latch data generated by one group of logic gates for use by a next group of logic gates during the next cycle time. The circuit implemented by a group of combinational logic gates interconnected between flip-flops is commonly called a "sequential machine". These static flip-flops are commonly master-slave edge-triggered flip-flops. However, as the speeds of these high performance circuits increase, the use of conventional master-slave edge-triggered flip-flops becomes unattractive because these conventional flip-flops are relatively slow and require both the true and complement of the clock signal. Typically, these conventional static flip-flops require special clock buffers or "headers" to generate complementary clock signals.
FIG. 1 is a schematic diagram of a typical conventional master-slave rising edge-triggered static flip-flop 100. The flip-flop 100 includes a master stage 101 driving a slave stage 103. The master stage 101 has a conventional transmission gate 105 having an input lead coupled to receive a data signal D. As is well known, the transmission gate 105 of the master stage is controlled to transmit the received data signal D by the true and complementary clock signals CK and CKB respectively received by the p-channel and n-channel devices implementing the transmission gate 105. Thus, the master stage's transmission gate 105 is controlled to pass the data signal D prior to a rising edge (i.e., while the clock signal CK is at a logic low level).
A conventional latch 107, implemented with the inverters INV1 and INV2, has an input lead connected to output lead of the transmission gate 105. Thus, while the clock signal CK is at a logic low level, the latch 107 inverts the data signal D and latches the inverted data signal on the output lead of the master stage 101. At the rising edge of the clock signal CK, the transmission gate 105 is no longer conductive, while the latch 107 continues to output the complement of the data signal D at the time of the rising edge.
The slave stage 103 also includes a transmission gate and a latch. However, the transmission gate 109 of the slave stage 103 is configured to be conductive when the transmission gate 105 is non-conductive and vice versa. Typically, the transmission gate of the slave stage is connected to receive the clock signals CK and CKB respectively at the gates of the n-channel and p-channel devices implementing the transmission gate 109. Thus, before the rising edge of the clock signal CK, the transmission gate 109 is non-conductive. However, at the rising edge of the clock signal CK, the transmission gate 109 transmits the latched output signal of the master stage 101 (i.e., the complement of the data signal D at the time of the rising edge) to a conventional output latch, implemented with the inverters INV3 and INV4. Thus, the output latch 111 outputs a signal Q equivalent to the data signal D at the time of the rising edge for the rest of the cycle. Counting the delay of the transmission gates as 1/2 of a typical gate delay, the conventional flip-flop 100 has a latency of about three gate delays, measured from the set-up time of the data signal D (prior to the rising edge of the clock signal CK) to the transition of the flip-flop output signal Q after the rising edge of the clock signal CK.
This latency represents a substantial portion of the cycle time of a high-performance synchronous very large scale integration (VLSI) system. For example, in a high performance microprocessor, a latency of two to three gate delays may represent up to 20% of the cycle time. Further, because the conventional flip-flops used in these high performance synchronous systems do not perform a logic operation (i.e., the flip-flops merely latch data), the latency of the flip-flop can be considered "overhead" that reduces the performance of the system. Still further, as clock speeds increase, fewer logic gates are used between flip-flops, thereby increasing the significance of this overhead.